Many-Core Architectures and Reconfiguration (Theme 3)

Initial Objectives

  • The development of hardware support for energy and reliability monitoring and control.
  • The development of customised memory subsystem support.
  • Research into new circuit-level techniques to improve energy/reliability trade-off.
  • Design automation flows and analysis for energy and reliability.


Computer architecture is in a tumultuous period. It has long been known that single thread scaling of execution speed is unsustainable due to energy consumption. Combined with advances in graphics processing, this led to the emergence of ‘general purpose graphics processing units’ (GPGPU) which emphasise maximising throughput of computation. Essentially the conventional wisdom is turned on its head: instead of one computation to be run as quickly as possible, GPUs excel in executing thousands of identical tasks: each one is relatively slow to execute, but the overall throughput is much greater. This change has been dubbed “the end of denial architecture” by Bill Dally, nVidia’s CTO.

However, Amdahl’s law is clear that the acceleration that can be gained from such an approach is fundamentally limited, and therefore the future of computer architecture is likely to be increasingly heterogeneous, combining throughput-processing engines with latency-optimized engines and special purpose accelerators with customised memory support in a system-on-chip. This is a complex picture: researchers are only beginning to explore the design of and compilation to such systems and many research challenges are posed.

At the same time as we move towards heterogeneous computing engines, the physics of the basic materials from which we produce our computer architectures in impinging ever more on the design of such systems. Very small feature sizes result in increasing effects of process variation, reliability, and increased ageing effects. If CMOS technology continues as the major implementation medium, then these effects will become more marked in the future; if CMOS technology is replaced by one of the many possible alternatives under research, these effects are likely to be even more pronounced. Thus any forward-looking architectural developments must incorporate methods to reason about and mitigate the impact of physical imperfection.

This theme is led by George Constantinides (Imperial), with individual workpackages led by investigators across institutions. The theme’s research will be tackled by PDRAs at Imperial, Manchester and Newcastle.

Key Outputs and Connections to Other Themes

The outputs from this theme include: FPGA-based IP cores for online circuit timing measurement and for activity-based emulation of energy measurement; tape out of instrumented big.LITTLE processor core for test purposes; an polyhedral analysis tool, reporting static analysis of memory access patterns, based on the LLVM compiler framework; an extension of the analysis tool to stochastic reasoning in the case of partial knowledge of memory access sequences; demonstrator on the hardware platforms showing the impact of the memory subsystem innovations on the energy/reliability trade-off; IP generators for customised arithmetic components and lightweight datapath redundancy; API and IP library for assertion synthesis; published integrated models of reliability/energy interplay incorporating the prior work referred to above into the framework developed in Theme 1; software to automatically propose instrumentations for model fidelity refinement, based on optimal DOE; initial multi-stage design automation tool to automatically determine appropriate architectural decisions and hooks provided to the next design stage.

Theme 3 is linked to other PRiME themes in the following ways. Theme 3 will work closely with Theme 1 (Cross-Layer Theory and Models) in the development of the models that will support the design automation tools and to ensure the fidelity of the models developed through instrumentation. Theme 3 will provide the necessary hooks and monitors to enable Theme 2 (High Integrity Run-time Management and Optimisation) to develop operating system and run-time optimization support. Theme 3 will deliver the Intellectual Property that will run on the platform designed in Theme 4 (Platforms, Applications and Demonstrators) , and will work closely with Theme 4 to ensure that the necessary support is provided by the platform.