KOCL Tool Download

KOCL (KAPow for OpenCL) is PRiME’s automated tool flow for generating FPGA designs capable of accelerating OpenCL kernel execution while reporting their own power consumptions.

In a modern FPGA system-on-chip design, it is often insufficient to simply assess the total power consumption of the entire circuit by design-time estimation or runtime power rail measurement. Instead, to make better runtime decisions, it is desirable to understand the power consumed by each individual module in the system.

KOCL is the first tool capable of generating hardware systems from OpenCL descriptions that are able to report their own kernel-level power consumption. The tool is general-purpose — it can be used with any OpenCL design that targets an Altera/Intel FPGA — and accessible thanks to its ease of application. While the principles of KOCL are generic, the current implementation is Altera/Intel-specific; it relies upon that vendor’s compilation tools and features optimisations for their FPGAs.

KOCL combines Altera’s OpenCL compiler with a refined version of PRiME’s existing KAPow (‘K’ounting Activity for Power estimation) flow, which requires no user exposure to, or understanding of, hardware, and enables easy access to live kernel-level power consumption from OpenCL host code.

(For an introduction to KaPOW see here – http://cas.ee.ic.ac.uk/people/gac1/pubs/EddieFCCM16.pdf )

The KOCL tool is being made available as a free, open-source software download. Further information and the tool downloads are available at: