DVFS Demonstration Experiment

Josh Levine, PhD researcher (Imperial College London) working within PRiME Theme 3 has prepared the following video to show Dynamic Voltage Frequency Scaling with online slack measurement.

The demonstrator shows that it is possible to achieve real-time monitoring of timing slack within arbitrary FPGA circuits. Josh and the team have created an automated tool flow for adding timing instrumentation to FPGA designs, demonstrated closed-loop, dynamic voltage and frequency scaling based on timing measurement. This can optimise throughput or power against voltage, power or throughput constraints.